1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus.
2. Related Art
In general, a semiconductor memory apparatus generates an internal voltage which has a voltage level necessary for an internal circuit, by using an external voltage. In order to allow the internal circuit to normally perform an operation, the semiconductor memory apparatus is designed such that the internal voltage level is stabilized to a target level within a preset time after the external voltage is initially applied to the semiconductor memory apparatus.
As a semiconductor memory apparatus is highly integrated, a gap between signal lines or power lines decreases, and thus, the parasitic capacitance between the lines increases. Accordingly, even through the internal voltage is generated to the target level in an internal voltage generation circuit of the semiconductor memory apparatus, the internal voltage of the target level is not transferred to the internal circuit due to the parasitic capacitance between the power lines for transferring the internal voltage to the internal circuit, whereby the misoperation of the semiconductor memory apparatus can be caused.